This invention relates to input/output data buffer apparatus for use with digital computers and digital data processors for buffering the transfer of data between peripheral input/output devices and a main storage unit associated with the digital computer or data processor.
A first problem encountered in the transfer of data between a peripheral input/output device and a data processor main storage unit is the difference in the length of the data segments passed to or received from the input/output device and the length of the data segments capable of being written into or read out of the main storage unit during a single access. Typically, the input/output device supplies data to or receives data from the data processor channel unit one byte at a time. Typically, the main storage unit is constructed to read or write eight bytes of data at a time. Known solutions to this problem are described in the above-listed U.S. Pat. Nos. 3,488,633 to King et al and 3,432,813 to Annunziata et al. These patents respectively describe the selector type channel unit and the multiplexer type channel unit used with the larger System/360 data processors manufactured by International Business Machines Corporation of Armonk, N.Y. In the channel units described in these patents, discrete hardware registers are used to assemble the bytes received one at a time from the input/output device. After enough bytes are accumulated to reach a storage word boundary, the assembled bytes are transferred as a group to the main storage unit. A converse procedure is followed when data is being transferred from the main storage unit to the input/output device.
The above-listed U.S. Pat. No. 3,643,221 to Chambers describes the channel buffer used in the System/370 Model 145 data processor manufactured by International Business Machines Corporation of Armonk, N.Y. In this processor, the transfer of data between the channel buffer and the main storage unit is done in four-byte, as opposed to eight-byte, segments. This channel buffer is a special type of eight-byte shift register characterized by the ability of data in each byte position to be alternatively not shifted, shifted one byte position or shifted two byte positions to the right, depending upon the full or empty conditions of the two succeeding byte positions. Data bytes received from an input/output device are entered at the left end of the shift register and the data bytes transferred to the main storage unit are taken in parallel from the rightmost four byte positions of the shift register. Conversely, when transferring data to the input/output device, the data from the main storage unit is entered in parallel into the leftmost four byte positions of the shift register and the data transferred to the input/output device is taken one byte at a time from the right end of the shift register.
The Capowski et al. U.S. Pat. No. 3,699,530, describes the channel buffer system used with the System/370 Model 165 data processor manufactured by International Business Machines Corporation of Armonk, N.Y. In this case, multiple buffers are provided for each input/output channel.
The Furlong U.S. Pat. No. 3,249,924, describes a channel buffer in the form of a one-byte wide core storage array capable of holding up to sixteen bytes of data per channel. The data bytes are transferred one at a time from the buffer to an eight-byte assembly register from whence they are transferred as a group to the main storage unit after the complete storage word is assembled in such register. The process of transferring the bytes to the assembly register is temporarily interrupted when an input/output device service request is received from a channel unit.
The mechanisms described in the patents discussed up to this point operate quite satisfactorily for their intended purposes. They are, however, not entirely suitable for use in very high-speed data processing systems having much higher data rates than those encountered in most systems currently in use. A limitation in many of the currently used systems is the time required to do the housekeeping and background chores needed to prepare the main storage unit to do the actual reading or writing of data. Thus, to obtain a higher data rate, a larger number of data bytes should be transferred to or from the main storage unit for any given performance of the background chores. In the embodiment to be described herein, up to sixty-four bytes of data are transferred between the data buffer and the main storage unit during each storage transfer operation or, in other words, for each performance of the background chores. Physically, the data is moved in eight-byte segments with up to eight such segments being transferred during any single storage transfer operation. On the average, this provides a significant reduction in the overall time required for storage transfer operations.
In order to enable these larger amounts of data to be transferred to or from the main storage unit in a very short interval of time, the channel data buffer must provide considerably more data buffering than is provided in the above-described data buffers. In other words, the storage capacity of the data buffer must be considerably greater. For reasons of economy and the like, this increased buffering capacity is preferably provided by using a semiconductor integrated circuit type storage array as the data buffer. The use of a storage array as a channel data buffer, however, presents data alignment problems relative to the data processor main storage unit.
For purposes of transferring data from a channel buffer storage array to the main storage unit, for example, the data read out of the channel buffer array during a single access should have the same boundary alignment as is needed by the main storage unit. This can be accomplished by the proper placement of data in the buffer array. This, however, complicates the transfer of data from the channel unit to the buffer array. It would be better and easier to simply pack the data from the channel unit into the buffer array in the order in which it is received and without regard to any main storage alignment requirements. Also, when the data in the channel buffer array is main storage aligned, the data chaining capability is poor. Thus, the packing of data into the buffer array without arbitrary gaps caused by main storage alignment restrictions would also improve the data chaining capability.
Similar considerations apply where the data is being transferred in the opposite direction, namely, from the main storage unit to the channel unit.
The above-listed U.S. Pat. Nos. 3,380,030 to McMahon and 3,626,376 to Anderson et al address the problem of data alignment when transferring data between a channel data buffer memory and a main storage unit. The McMahon patent describes a gating and hardware register arrangement for transferring data between two storage units having different storage word lengths or data access lengths. Two machine cycles or storage access operations are required to complete a transfer when the data to be transferred lies on two different rows in the source storage unit. Among other things, the McMahon apparatus is slower and requires more control hardware than is desired for present purposes.
The Anderson et al patent describes a skewing circuit for skewing to the right data bytes being transferred from the data buffer memory to the main storage unit when the starting byte position in the main storage unit lies to the right of the leftmost byte position. A hardware register is provided for catching and holding any bytes which are skewed past the right-hand boundary of the main storage unit. On subsequent transfers, data is transferred simultaneously from the data buffer and the hardware register to form a complete word for storage in the main storage unit, any used bytes from the data buffer being thereafter entered into the hardware register and saved for a subsequent main storage access. Unfortunately for present purposes, the Anderson et al apparatus requires the use of an additional hardware register and, in addition, does not take into account the case where the starting byte position in the data buffer is not the leftmost byte in the data buffer.
Though making no mention of channel data buffers, U.S. Pat. Nos. 3,602,896 to Zeheb and 3,916,388 to Shimp et al are of interest in that they relate to the alignment of data being transferred to or from a main storage unit, the data in these cases being sent to or received from the instruction processing unit. The Zeheb patent describes a three-dimensional core-type random access main storage unit having a four-byte storage word or storage access length and core drive line control circuitry whereby the four bytes being accessed may start on any byte position of a four-byte storage word. Thus, the accessed four-byte data word may overlap one storage word boundary into an adjacent storage word. This circumvents the storage alignment problem and enables any four contiguous bytes to be accessed during a single storage access.
The Shimp et al patent describes an eight-byte data shifter for automatically aligning a multibyte data segment accessed from a main storage unit so that it may be loaded into a processor register in a right-justified manner. Conversely, it also automatically shifts data taken from a processor register so that it will have the proper alignment when it is set into the main storage unit. Two main storage access operations are required when the data segment lies across a storage word boundary. This data shifter is of particular interest in that, as will be seen, it can also be used to provide the data shifting action used in connection with the present invention.
The above-cited prior art patents represent what applicant considers to be the best of the prior art presently known to him. No representation is made or intended, however, that better prior art does not exist. Nor is any representation made or intended that the foregoing interpretations are the only interpretations that can be placed on this prior art.